MOSFETs use embedded silicon germanium (eSiGe) or embedded silicon carbon (eSiC) as the source/drain stressor for PMOS or NMOS, respectively. These embedded stressors are grown epitaxially after a recess etch into the source/drain regions is performed. For a source/drain region bounded by a shallow trench isolation (STI) structure, the outer edge of the source/drain region includes the STI material (e.g., oxide) rather than the substrate material. This leads to a faceted growth of the embedded stressor material.
The faceted growth can be severe enough such that the final, grown source/drain thickness is thinner than in unbound regions (i.e., bound only by substrate material along the source/drain periphery). This leads to a greater proximity between the source/drain junction and the contact material which, in turn, leads to high junction leakage. Also, the reduced volume resulting from the faceted growth leads to reduced stress, which reduces device performance.
In order to circumvent these penalties, an STI edge can be tucked under an adjacent dummy gate. This dummy gate effectively serves as a spacer to mask some substrate material adjacent to the STI edge during the source/drain recess etch, such that subsequent epitaxial growth is bound by substrate material on all sides (leading to the desired epitaxial growth). In this approach, though, the dummy gate imposes an additional parasitic capacitance to the source/drain regions, which increases circuit delay and dynamic power consumption. Moreover, a layout area penalty is imposed, since the active region spacing is linked to the gate pitch. Also, this approach is a 1-D solution in that it only resolves the faceting issue in the length direction (i.e., in the direction perpendicular to the gate) but not the width direction.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.